1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, such as a dynamic random access memory (DRAM) of a CMOS type.
2. Description of the Related Art
In a CMOS integrated circuit, an NMOS transistor and a PMOS transistor are formed in an isolated manner by use of a wafer wherein a first-conductivity type semiconductor substrate has a second-conductivity type well formed therein A DRAM is one example of such a CMOS integrated circuit. Many of conventional CMOS-DRAMs employ a p-type silicon substrate. This is the DRAMs can be manufactured at low cost since the p-type silicon substrate is lower in price than the n-type silicon substrate.
In the case where an NMOS DRAM cell is fabricated by use of a p-type substrate, it is general that a negative substrate bias V.sub.BB (normally, -2 V or thereabouts) is applied to the p-type substrate because application of such the negative substrate bias not only reduces the bit line capacitance which is due to the reduction of a p-n junction capacitance but also improves the cut-off characteristic of a cell transistor. Therefore, the NMOS transistor is designed such that its threshold voltage takes an optimal value at the time of application of the substrate bias V.sub.BB.
If the NMOS transistor is designed in this manner, the threshold voltage of the NMOS transistor is low immediately after the power supply is turned on since the substrate bias is 0 V at the time. It may therefore happen that the circuit cannot be initialized due to a large amount of penetration current flowing through peripheral circuits. This problem is serious if the MOS transistor is miniaturized since, in the case where the MOS transistor is miniaturized, the impurity concentration of the substrate portion corresponding to an NMOS transistor region has to be increased for suppressing the short channel effect and the substrate bias effect is inevitably increased thereby.
In recent years, n-type silicon substrates have come to be employed in more and more CMOS-DRAMs. The employment of the n-type silicon substrates is advantageous in the following points:
First, the data retaining characteristic of a DRAM cell can be improved. The reason for this improvement is that, where a DRAM cell array is provided in a p-type well formed in an n-type silicon substrate, the DRAM cell is protected by the pn junction formed between the n-type substrate and the p-type well. To be more specific, part of the electrons that are generated by the irradiation of c-rays are attracted toward the n-type substrate, not toward the DRAM cell, with the result that the soft error durability is improved. In addition, the damage to cell data due to the undershoot of input pins or due to the minority carriers generated from the n-channel MOS transistors of the peripheral circuits, can be prevented.
Second, the core circuit portion including the DRAM cell array and the p-type well of a peripheral circuit can be isolated from each other, and different bias voltages can be applied thereto. For example, the p-type well of the DRAM cell array region can be applied with a negative voltage V.sub.BB, while the p-type well of the peripheral circuit portion can be set at the ground potential level. When the power supply is turned on, therefore, a large amount of penetration current is prevented from flowing through peripheral circuits, since the threshold voltage of the NMOS transistors of the DRAM cell array and that of the NMOS transistors of the peripheral circuit portion can be optimally determined in accordance with the bias voltages of their respective p-type wells.
However, in the case where the DRAM is fabricated by use of the n-type silicon substrate in the manner stated above, the voltage at the p-type well of the core circuit portion transiently increases when the power supply is turned on, due to the capacitive coupling between that p-type well and the substrate. Such a transient voltage increase at the p-type well gives rise to disadvantages to the characteristics of the DRAM. One of the disadvantages is: if the p-type well containing a DRAM cell array formed therein has grounded n-type diffusion layers, a large amount of penetration current inevitably flows, due to the existence of parasitic bipolar transistors. Another disadvantages is: if the p-type well does not have an n-type diffusion layer which is grounded, a long time is required for the DRAM to start a normal operation after the power supply is turned on. These two disadvantages will be explained in more detail, with reference to the drawings.
FIG. 13 is a sectional view showing the major portion of a DRAM chip that employs an n-type substrate 1. A p-type well 2 is formed in the cell array region of the n-type substrate 1, and memory cells each made up of an NMOS transistor QM and a capacitor CM are formed in the p-type well in an array. N-type diffusion layers 3 and 4, which serve as the source and drain of the NMOS transistor QM, respectively, are storage nodes and connected to a bit line. A trench is formed in the vicinity of the n-type diffusion layer 3, which is a storage node, and a plate electrode 5 is embedded in the trench, thereby forming a capacitor CM. An NMOS transistor Q1, with which to ground a word line nonselected, is normally formed in the p-type well 2 wherein the DRAM cell array is formed.
A p-type well 6 and an n-type well 7 are formed in the peripheral circuit region, so as to provide an NMOS circuit and a PMOS circuit. In FIG. 13, one NMOS transistor Q3 is depicted as being formed in the p-type well 6, and one PMOS transistor Q2 is depicted as being formed in the n-type well 7.
In an normal operation mode, the p-type well 2 of the DRAM cell array region is applied with a negative bias voltage V.sub.BB from a V.sub.BB voltage generating circuit 11. The plate electrode of the DRAM cell is applied with a bias voltage V.sub.PL from a plate voltage generating circuit 12, and the bit line is applied with a bias voltage V.sub.BL from a bit line voltage generating circuit 13 at the time of precharge. The p-type well 6 of the peripheral circuit portion is grounded, and the n-type well 7 thereof is connected to power supply V.sub.CC.
In the circuit arrangement mentioned above, a parasitic npn transistor T is inevitably formed by an n-type diffusion layer 8 (which is connected to a ground potential point of the NMOS transistor Q1), the p-type well 2, and the n-type substrate 1. After the power supply V.sub.CC is turned on, the p-type well 2 of the core circuit portion is kept floated for a certain time until the V.sub.BB voltage generating circuit 11 begins to operate in a normal manner. Since, therefore, the voltage at the p-type well 2 is increased due to the capacitive coupling at the pn junction between the substrate 1 and the p-type well 2, the voltage becomes positive. Accordingly, when the parasitic transistor T becomes ON, a large amount of penetration current flows between V.sub.CC and V.sub.SS.
The above-mentioned parasitic bipolar transistor is not formed in the case where the p-type well 2 does not contain a grounded n-type diffusion layer, such as the NMOS transistor Q1 provided for grounding the word line non-selected Even in this case, an increase in the voltage at the p-type well still produces a problem.
As long as there is a grounded n-type diffusion layer (even if this diffusion layer has a very small area in comparison with the area of the p-type well 2), an increase in the voltage at the p-type well is suppressed because a pn junction current flows out. In contrast, in the case where there is no grounded n-type diffusion layer, the pn junction current does not flow at all. Hence, a long time is required for the voltage at the p-type well 2 to reach the negative bias voltage V.sub.BB (i.e., the voltage value determined at the time of design), after the V.sub.BB voltage generating circuit begins to operate.
As mentioned above, in the conventional CMOS-DRAM employing an n-type substrate, the bias voltage generating circuit is connected to the p-type well where the DRAM cell array is formed. Since, in the CMOS-DRAM, the p-type well is kept floated for a certain period after the power supply is turned on, the voltage at the p-type well transiently increases. Due to this transient voltage increase, the parasitic bipolar transistor becomes ON, resulting in the flow of a large amount of penetration current Even if the parasitic bipolar transistor does not become ON, a long time is required before the CMOS-DRAM can operate in a normal manner (i.e., the delay time is lengthened).
The problems mentioned above are not peculiar to a DRAM; they may occur in circuits of other types, such as a CMOS circuit, as long as the circuits have a similar well structure to that of the above-mentioned DRAM.